LocalBus

LocalBus is a custom bus interface. You can use it for your register map, hovewer, it was designed specially to simplify integrating more common bus interfaces to register map. It acts as internal “virtual” interface.

In fact, all other supported buses (APB, AXI-Lite and etc.) in corsair are nothing more than just bridges to LocalBus interface under the hood.

Signals

Signal

Width

Direction

Description

waddr

>1

input

Write address bus

wdata

>1

input

Write data bus

wen

1

input

Write request enable signal

wstrb

>1

input

Write byte strobe bus (one bit for every write data byte)

wready

1

output

Write request ready signal

raddr

>1

input

Read address bus

ren

1

input

Read request enable signal

rdata

>1

output

Read data bus

rvalid

1

output

Read data valid signal

Note

Specific bit widths for buses are defined in globcfg section of a csrconfig file.

Transfers

Only simple single transfers are supported. No bursts or stream accesses. Every transfer can be extended with special signals.

Just for example, data bus is 32 bits wide for all the waveforms below.

Simple write

Write data D0 to address A0.

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Write with bytes strobes

Byte strobe signalling to write only bytes 1 and 2 (wstrb = 0x6 = 0b0110) of D0 word.

_images/wavedrom-a6427a22-5062-442b-93b7-ef169b2ebdd9.svg

Write with wait states

Write data D0 to address A0, then write D1 to A1 ends (wen goes low) as soon as wready become high.

_images/wavedrom-47775a4d-e319-4184-a863-1d100d8f905d.svg

Simple read

Read data D0 from address A0. Minimum response time - 1 tick. “Combinatoral” (in the same tick) read is not supported. Read ends (ren goes low) after rvalid is asserted.

_images/wavedrom-9bbfa1fb-05c0-423b-a4bd-481473a3a977.svg

Read with wait states

Read data D0 from address A0 with 2 wait states.

_images/wavedrom-8f1e3ffa-0a1a-4760-b4bb-7d6d37687180.svg